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Clock Domain Crossing (CDC) Protocol

A set of design rules and synchronizers (e.g., two-flip-flop synchronizer) required when signals pass between circuits operating at different clock frequencies to prevent metastability.
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The statement of the theorem

When a signal SS crosses from a domain clocked by CLK1\text{CLK}_1 to a domain clocked by CLK2\text{CLK}_2, a synchronizer is required. The standard two-flip-flop synchronizer uses the following structure: Ssync,1=D (on CLK2 edge)S_{sync, 1} = D \text{ (on } \text{CLK}_2 \text{ edge)} and Ssync,2=D (on CLK2 edge)S_{sync, 2} = D \text{ (on } \text{CLK}_2 \text{ edge)}. The output SoutS_{out} is taken from Ssync,2S_{sync, 2}. This structure mitigates metastability by allowing the signal to settle over two clock cycles.